Generate ONLY the Verilog module code for the following specification.

## Problem Description
Design a dual-port register file for a small soft processor. The register file contains 32 registers, each 32 bits wide. It provides two independent read ports and one write port. Reads are combinational, and writes are synchronous on the rising edge of the clock when write enable is asserted. If a read address matches the write address in the same cycle, the read must return the write data (write has priority).
Register 0 is a hardwired zero register. Reads from address 0 must always return 32'b0, and writes to address 0 must be ignored.
RESET: Synchronous active-high reset. When rst=1, all registers are cleared to 0 on the next rising edge.


## Interface Specification
Module Name: register_file_2r1w
Ports:
  - input 1 clk // Clock
  - input 1 rst // Synchronous active-high reset
  - input 5 raddr1 // Read address for port 1
  - input 5 raddr2 // Read address for port 2
  - output 32 rdata1 // Read data for port 1
  - output 32 rdata2 // Read data for port 2
  - input 1 we // Write enable
  - input 5 waddr // Write address
  - input 32 wdata // Write data

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module register_file_2r1w` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable