Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a G-Share branch predictor with 7-bit PC and 7-bit global history register (GHR). The PC and GHR are XORed together to form a 7-bit index into a 128-entry Pattern History Table (PHT). Each PHT entry is a 2-bit saturating counter: 00 = strongly not-taken, 01 = weakly not-taken,  10 = weakly taken, 11 = strongly taken. Prediction is taken if counter[1] == 1.
The predictor has two independent interfaces: prediction (fetch stage) and training (execute stage).
PREDICTION (predict_valid=1): Given predict_pc, compute PHT index = predict_pc XOR current_GHR. Output the prediction (predict_taken) and the GHR value used (predict_history). At the next  positive clock edge, update GHR by shifting in the predicted direction.
TRAINING (train_valid=1): Given train_pc, train_history (GHR at prediction time), train_taken  (actual outcome), and train_mispredicted flag. Compute PHT index = train_pc XOR train_history. Update the corresponding PHT counter based on train_taken (increment if taken, decrement if not,  saturating at 00 and 11). If train_mispredicted=1, also recover the GHR to {train_history[5:0], train_taken}.
SIMULTANEOUS OPERATIONS: - Training takes priority over prediction for GHR updates when both occur in the same cycle. - PHT is updated at the positive clock edge, so prediction sees the pre-training state if both 
  access the same PHT entry in the same cycle.

RESET: Asynchronous active-high reset (areset) clears all PHT entries to 2'b01 (weakly not-taken)  and GHR to 7'b0.


## Interface Specification
Module Name: gshare_predictor
Ports:
  - input 1 clk // Clock signal
  - input 1 areset // Asynchronous active-high reset
  - input 1 predict_valid // Prediction request valid
  - input 7 predict_pc // Program counter for prediction (lower 7 bits)
  - output 1 predict_taken // Predicted branch direction (1=taken, 0=not-taken)
  - output 7 predict_history // Global history register value used for this prediction
  - input 1 train_valid // Training request valid
  - input 1 train_taken // Actual branch outcome (1=taken, 0=not-taken)
  - input 1 train_mispredicted // Branch was mispredicted, requires GHR recovery
  - input 7 train_history // GHR value used when the branch was originally predicted
  - input 7 train_pc // Program counter of the branch being trained

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module gshare_predictor` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable