Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a high-throughput pipelined AES-128 encryption module for FPGA. Input: 128-bit plaintext and 128-bit key, with valid signal per block. Perform AES-128 encryption (10 rounds) following FIPS-197 standard. Use a fully pipelined architecture with Initiation Interval (II) = 1, meaning a new input block can be accepted every clock cycle. Output: 128-bit ciphertext with valid_out signal when result is ready. Latency may be multiple cycles, but throughput must be 1 block per cycle. The key can be considered constant (load once, encrypt many blocks). Use standard AES S-box and MixColumns operations.


## Interface Specification
Module Name: aes128_pipelined
Ports:
  - input 1 clk
  - input 1 rst
  - input 128 key
  - input 128 plaintext
  - input 1 valid_in
  - output 128 ciphertext
  - output 1 valid_out

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module aes128_pipelined` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable