Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement an AES-128 encryption module for FPGA. Input: 128-bit plaintext and 128-bit key loaded via a 32-bit data port. Perform AES-128 encryption (10 rounds) following FIPS-197 standard. Output: 128-bit ciphertext via a 32-bit data port. Interface: Load key in 4 cycles (32 bits each), load plaintext in 4 cycles, assert 'start' to begin encryption, module asserts 'done' when ciphertext is ready. Read ciphertext in 4 cycles (32 bits each). Use standard AES S-box and MixColumns operations.


## Interface Specification
Module Name: aes128_encrypt
Ports:
  - input 1 clk
  - input 1 rst
  - input 1 load_key
  - input 1 load_data
  - input 32 data_in
  - input 1 start
  - output 32 data_out
  - input 1 read_data
  - output 1 done
  - output 1 busy

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module aes128_encrypt` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable