Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a Sobel edge detection accelerator for FPGA. Input: 64x64 grayscale image (1 channel, 8-bit unsigned pixels, row-major streaming). Apply standard 3x3 Sobel kernels to compute horizontal (Gx) and vertical (Gy) gradients. Gx kernel: [[-1,0,1], [-2,0,2], [-1,0,1]]. Gy kernel: [[-1,-2,-1], [0,0,0], [1,2,1]]. Compute gradient magnitude using |Gx| + |Gy| approximation (saturate to 0-255). Use stride 1 and zero-padding 1 to produce 64x64 output feature map. Output: 8-bit unsigned gradient magnitude per pixel, row-major streaming. Module asserts 'done' for one cycle when complete.


## Interface Specification
Module Name: sobel_edge
Ports:
  - input 1 clk
  - input 1 rst
  - input 1 start
  - input 8 pixel_in
  - input 1 pixel_valid
  - output 1 pixel_ready
  - output 8 pixel_out
  - output 1 out_valid
  - input 1 out_ready
  - output 1 done

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module sobel_edge` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable