Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a small ternary content-addressable lookup engine with eight
entries. This style of masked lookup is commonly used in packet
classification and routing tables.

STORED TABLE:
- The module maintains 8 entries indexed 0 through 7.
- Each entry contains:
    - a valid bit
    - an 8-bit key
    - an 8-bit mask
    - an 8-bit associated value
- After reset, all 8 entries are invalid.

WRITE PORT:
- A write is accepted on each rising edge of `clk` for which `rst=0` and
  `wr_en=1`.
- `wr_addr` selects which entry is updated.
- If `wr_clear=0`, then on that rising edge the selected entry becomes valid
  and its key, mask, and value are replaced by `wr_key`, `wr_mask`, and
  `wr_value`.
- If `wr_clear=1`, then on that rising edge the selected entry becomes
  invalid. In that case `wr_key`, `wr_mask`, and `wr_value` are ignored.
- At most one entry is written per cycle.

LOOKUP RULE:
- `lookup_key` is compared against all currently stored valid entries.
- For entry `i`, a match occurs if and only if:
    `valid[i] = 1` and `((lookup_key ^ key[i]) & mask[i]) == 8'h00`
- Mask bit meaning:
    - `mask[i][b] = 1` means bit `b` must match exactly.
    - `mask[i][b] = 0` means bit `b` is don't-care.
- Therefore, a valid entry with `mask=8'h00` matches every `lookup_key`.

PRIORITY RULE:
- If one or more entries match, assert `match=1`.
- `match_idx` must be the lowest-index matching entry.
- `match_value` must be the associated value stored in that same selected
  entry.
- If no entries match, drive `match=0`, `match_idx=3'b000`, and
  `match_value=8'h00`.

TIMING:
- `match`, `match_idx`, and `match_value` are combinational outputs derived
  from the current table contents and the current `lookup_key`.
- There is no extra output register stage.
- Table state changes only on rising edges of `clk`.
- A write accepted on a rising edge becomes visible to the lookup outputs
  after that edge.

RESET:
- `rst` is synchronous and active-high.
- While `rst=1`, all entries must be cleared to invalid on the rising edge,
  `wr_en` must be ignored, and the outputs must be forced to
  `match=0`, `match_idx=0`, and `match_value=0`.
- After `rst` is deasserted, the table is empty until new writes occur.


## Interface Specification
Module Name: tcam8_lookup
Ports:
  - input 1 clk // System clock
  - input 1 rst // Synchronous active-high reset
  - input 8 lookup_key // 8-bit search key presented to all entries
  - input 1 wr_en // High to update one entry on the current rising edge
  - input 3 wr_addr // Index of the entry to write or clear
  - input 1 wr_clear // 1 clears the selected entry, 0 writes a valid entry
  - input 8 wr_key // Key stored into the selected entry when `wr_clear=0`
  - input 8 wr_mask // Mask stored into the selected entry when `wr_clear=0`; 1 means care, 0 means don't-care
  - input 8 wr_value // Associated value stored into the selected entry when `wr_clear=0`
  - output 1 match // High when at least one valid entry matches `lookup_key`
  - output 3 match_idx // Lowest-index matching entry, or 0 when no entry matches
  - output 8 match_value // Associated value from the selected matching entry, or 0 when no entry matches

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module tcam8_lookup` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable