Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a synchronous detector that identifies R-peak events from a
stream of preprocessed ECG amplitude samples.

Each rising edge of `clk` samples one unsigned 12-bit value on
`sample_in`. The input stream is already preprocessed; higher values
correspond to stronger candidate peaks. The module must examine a
5-sample window and emit a one-cycle `peak_out` pulse only for samples
that satisfy the rules below.

PEAK RULE:
- Let x[n] be the sample captured on cycle n after reset is deasserted.
- Let t[n] be the value of `threshold` captured on that same cycle n.
- A sample x[n] is a candidate peak only when all of the following are
  true:
    - x[n] is greater than or equal to t[n]
    - x[n] is strictly greater than x[n-2], x[n-1], x[n+1], and x[n+2]
- Plateaus are therefore not peaks. If any compared neighbour has the
  same value as x[n], the candidate must be rejected.

OUTPUT TIMING:
- Because the decision for x[n] depends on x[n+1] and x[n+2], the module
  cannot decide immediately.
- When the sample captured in cycle n is accepted as an R-peak,
  `peak_out` must be high for exactly one cycle on cycle n+2.
- In every other cycle, `peak_out` must be low.
- The first four sampled cycles after reset deassertion can never produce
  `peak_out`, because a full 5-sample window is not yet available.

REFRACTORY RULE:
- Accepted R-peaks must be separated by at least 50 sample intervals.
- If x[p] is the most recent accepted peak sample, then a later candidate
  x[n] may be accepted only when n - p >= 50.
- Any candidate with 1 <= n - p <= 49 must be rejected, even if it
  satisfies the amplitude and local-maximum conditions.
- The refractory rule is defined using the sample indices of the accepted
  center samples, not the later `peak_out` pulse cycles.

RESET:
- `rst` is synchronous and active-high.
- While `rst` is high, clear all sample history and refractory state, and
  drive `peak_out` low.
- After reset is deasserted, detection restarts from an empty history.


## Interface Specification
Module Name: ecg_r_peak_detector
Ports:
  - input 1 clk // System clock; one ECG sample is processed per cycle
  - input 1 rst // Synchronous active-high reset
  - input 12 sample_in // Unsigned preprocessed ECG amplitude sample
  - input 12 threshold // Unsigned minimum amplitude required for an accepted peak
  - output 1 peak_out // One-cycle pulse asserted when the sample from two cycles earlier is accepted as an R-peak

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module ecg_r_peak_detector` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable