Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a synchronous UART receiver for 8-N-1 serial frames.

FRAME FORMAT:
- Serial line `rx` is idle high.
- Each frame consists of:
    - 1 start bit = 0
    - 8 data bits, least-significant bit first
    - 1 stop bit = 1
- There is no parity bit.

BIT TIMING:
- One UART bit period is exactly 16 rising edges of `clk`.
- The receiver is idle while waiting for a potential start bit.
- A candidate start bit begins when the receiver is idle and observes
  `rx=0` on a rising edge of `clk`.
- Exactly 8 rising edges of `clk` after that detection edge, sample the
  middle of the start bit:
    - If `rx` is 0 at that midpoint sample, accept the frame.
    - If `rx` is 1 at that midpoint sample, treat it as a false start and
      return to the idle state with no output pulse.
- After a valid start bit, sample the 8 data bits every 16 rising edges of
  `clk`, beginning 16 rising edges after the start midpoint sample.
- Sample the stop bit 16 rising edges after the sample of data bit 7.

OUTPUT BEHAVIOUR:
- If the stop-bit sample is 1, pulse `data_valid` high for exactly one
  cycle and drive the received byte on `data_out`.
- If the stop-bit sample is 0, pulse `framing_error` high for exactly one
  cycle and do not assert `data_valid`.
- `data_valid` and `framing_error` must never be high in the same cycle.
- `data_out` is only required to be valid in cycles where `data_valid` is
  high.

RECEPTION RULES:
- While a frame is in progress, the receiver must ignore intermediate
  transitions on `rx` except at the defined sample points.
- Back-to-back valid frames are allowed. No extra idle cycles are required
  beyond the single stop bit.
- The benchmark will not present breaks, parity bits, or configurable baud
  rates.

RESET:
- `rst` is synchronous and active-high.
- While `rst` is high, clear any partial reception state and drive both
  `data_valid` and `framing_error` low.
- If `rst` is asserted in the middle of a frame, abandon that frame and
  return to the idle state immediately after that rising edge of `clk`.


## Interface Specification
Module Name: uart_receiver
Ports:
  - input 1 clk // System clock running at 16x the UART baud rate
  - input 1 rst // Synchronous active-high reset
  - input 1 rx // Asynchronous UART serial input, idle high
  - output 8 data_out // Received byte, valid only when data_valid is high
  - output 1 data_valid // One-cycle pulse for a correctly received frame
  - output 1 framing_error // One-cycle pulse when the stop bit is sampled low

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module uart_receiver` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable