Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a synchronous SPI master that performs one full-duplex
8-bit transfer at a time.

PROTOCOL SUBSET:
- SPI mode 0 only: `sclk` idles low, data changes while `sclk` is low,
  and input data is sampled on each rising edge of `sclk`.
- Each accepted transaction transfers exactly 8 bits.
- Bits are transferred most-significant bit first.

START AND TIMING:
- A transfer request is accepted on a rising edge of `clk` when
  `start` is high and `busy` is low.
- Immediately after an accepted request:
    - `busy` must be high
    - `cs_n` must be low
    - `sclk` must remain low
    - `mosi` must present `tx_data[7]`, the first bit to transmit
- While a transfer is active, `sclk` uses fixed timing:
    - on each subsequent rising edge of `clk`, `sclk` toggles
    - therefore the first toggle after an accepted request is a rising
      edge of `sclk`
    - one full `sclk` period is exactly 2 cycles of `clk`
- On each rising edge of `sclk`, sample the current value of `miso`.
  The first rising edge samples the most-significant received bit.
- On each falling edge of `sclk`, if more bits remain to be sent, update
  `mosi` to the next transmit bit while `sclk` is low.

COMPLETION:
- After the 8th rising edge of `sclk`, the received byte is complete.
- On the next rising edge of `clk` after that final sample:
    - `busy` must go low
    - `done` must pulse high for exactly one cycle
    - `cs_n` must return high
    - `sclk` must return low
    - `rx_data` must hold the assembled received byte
- `rx_data` is only required to be valid in cycles where `done` is high.

BUSY BEHAVIOUR:
- While `busy` is high, additional assertions of `start` must be ignored.
- While idle, `done` must be low, `cs_n` must be high, and `sclk` must
  be low.

RESET:
- `rst` is synchronous and active-high.
- While `rst` is high, the module must be idle: `busy=0`, `done=0`,
  `cs_n=1`, and `sclk=0`.
- If `rst` is asserted during a transfer, the transfer is aborted and
  the module returns to the idle state immediately after that rising
  edge of `clk`.


## Interface Specification
Module Name: spi_master_controller
Ports:
  - input 1 clk // System clock
  - input 1 rst // Synchronous active-high reset
  - input 1 start // Pulse high to request a new 8-bit transfer when idle
  - input 8 tx_data // Transmit byte, sent MSB first
  - input 1 miso // SPI input sampled on rising edges of sclk
  - output 1 mosi // SPI output driven MSB first
  - output 1 sclk // SPI serial clock in mode 0
  - output 1 cs_n // Active-low chip select
  - output 1 busy // High while a transfer is in progress
  - output 1 done // One-cycle pulse when rx_data is valid
  - output 8 rx_data // Received byte assembled from sampled miso bits

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module spi_master_controller` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable