Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a synchronous round-robin arbiter for eight input queues
competing for access to one shared output port.

The input `req[7:0]` is a level-sensitive request vector. Bit `i`
being high means requester `i` currently needs service.

OUTPUT SELECTION:
- If one or more request bits are high, assert `grant_valid` and drive
  `grant_idx` with the ID of the selected requester.
- The selected requester must be the first active requester found in
  round-robin order, starting from the current highest-priority
  requester and wrapping around from 7 back to 0.
- After reset, the priority order starts at requester 0, then 1, 2,
  3, 4, 5, 6, 7, then wraps.

ACCEPTED GRANTS:
- A grant is accepted on a rising clock edge when both `grant_valid`
  and `grant_ready` are high.
- If requester `k` is granted in an accepted cycle, then on
  subsequent cycles the round-robin search must start from requester
  `(k + 1) mod 8`.
- If no grant is accepted in a cycle, the current priority order must
  remain unchanged.

REQUEST AND STALL BEHAVIOUR:
- Requests are level-sensitive, not pulses.
- A requester may remain asserted across multiple cycles until it is
  serviced.
- If `grant_ready` is low, no grant is accepted and the fairness order
  must not advance.
- If only one requester is active, it may be selected on every
  accepted cycle.

IDLE AND RESET:
- If all request bits are low, `grant_valid` must be low. In that
  case, `grant_idx` is don't-care and will not be checked.
- `rst` is synchronous and active-high.
- While `rst` is high, `grant_valid` must be low regardless of the
  value of `req`.
- While `rst` is high, `grant_idx` is don't-care and will not be
  checked.
- On reset, restore the initial round-robin priority.
- On the first cycle after `rst` is deasserted, arbitration resumes
  from requester 0 using the current `req` vector.

TIMING:
- Arbitration state updates only on rising clock edges.
- `grant_valid` and `grant_idx` must reflect the current request
  vector and the current round-robin priority with no extra output
  register stage.


## Interface Specification
Module Name: round_robin_arbiter
Ports:
  - input 1 clk // Clock signal
  - input 1 rst // Synchronous active-high reset
  - input 8 req // Request vector from the eight input queues
  - input 1 grant_ready // High when the downstream path accepts the selected requester this cycle
  - output 1 grant_valid // High when at least one requester is currently eligible for service
  - output 3 grant_idx // ID of the selected requester

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module round_robin_arbiter` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable