Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement an AXI4-Stream upsizer that converts an 8-bit input stream into a 32-bit output stream.
The module accepts one byte at a time on the slave AXI4-Stream interface and packs consecutive input bytes into a single 32-bit output word on the master AXI4-Stream interface.
AXI4-STREAM HANDSHAKE: - An input transfer occurs on a rising clock edge when both
  `s_axis_tvalid` and `s_axis_tready` are high.
- An output transfer occurs on a rising clock edge when both
  `m_axis_tvalid` and `m_axis_tready` are high.
- When `m_axis_tready` is low, the module must hold any pending output
  word stable and must apply backpressure on the input side whenever
  it cannot accept additional bytes.

DATA PACKING: - The first accepted byte of an output word is stored in bits [7:0]. - The second accepted byte is stored in bits [15:8]. - The third accepted byte is stored in bits [23:16]. - The fourth accepted byte is stored in bits [31:24]. - After four bytes have been accepted, `m_axis_tvalid` must assert to
  present the packed 32-bit word.

PACKET BOUNDARIES: - `s_axis_tlast` marks the final byte of an input packet. - If `s_axis_tlast` is accepted before four bytes have been collected,
  the module must make the partial 32-bit word available on the output
  immediately after that accepting clock edge, with no extra flush
  cycle.
- Any unused byte lanes in a partial output word must be filled with
  zeros.
- `m_axis_tkeep` indicates which output byte lanes are valid:
    4'b0001 = 1 valid byte
    4'b0011 = 2 valid bytes
    4'b0111 = 3 valid bytes
    4'b1111 = 4 valid bytes
- `m_axis_tlast` must be asserted on the output word that contains the
  final byte of the input packet.

RESET: - `rst` is synchronous and active-high. - On reset, clear any partially collected input bytes, deassert all
  output valid signals, and return the module to its idle state.


## Interface Specification
Module Name: axis_width_converter
Ports:
  - input 1 clk // Clock signal
  - input 1 rst // Synchronous active-high reset
  - input 8 s_axis_tdata // Input AXI4-Stream data byte
  - input 1 s_axis_tvalid // Input AXI4-Stream valid
  - output 1 s_axis_tready // Input AXI4-Stream ready
  - input 1 s_axis_tlast // Input end-of-packet marker
  - output 32 m_axis_tdata // Packed output AXI4-Stream word
  - output 4 m_axis_tkeep // Output byte-valid mask
  - output 1 m_axis_tvalid // Output AXI4-Stream valid
  - input 1 m_axis_tready // Output AXI4-Stream ready
  - output 1 m_axis_tlast // Output end-of-packet marker

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module axis_width_converter` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable