Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement an 8-tap symmetric low-pass FIR filter. Input: 8-bit signed. Output: 16-bit signed. Symmetric coefficients (H[k] = H[7-k]): H0=8, H1=21, H2=45, H3=54. Design must achieve single-cycle throughput (Initiation Interval = 1).


## Interface Specification
Module Name: fir_8tap
Ports:
  - input 1 clk
  - input 1 rst
  - input 8 sample_in
  - input 1 in_valid
  - output 16 sample_out
  - output 1 out_valid

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module fir_8tap` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable