Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a clocked hardware module that computes a 4-point complex discrete
Fourier transform (DFT) on one input frame at a time.

Each frame consists of four complex input samples presented over four
consecutive clock cycles while `in_valid` is high. The first valid sample of a
frame is `x0`, followed by `x1`, `x2`, and `x3`. Each sample uses signed
12-bit two's-complement real and imaginary components.

For each frame, compute the complex outputs `X0` through `X3` according to:

  X[k] = sum for n=0..3 of x[n] * W4^(k*n)

where `W4 = exp(-j*2*pi/4)`.

The equivalent output relations are:

  X0 = x0 + x1 + x2 + x3
  X1 = x0 - j*x1 - x2 + j*x3
  X2 = x0 - x1 + x2 - x3
  X3 = x0 + j*x1 - x2 - j*x3

The transform must be exact for the given integer input values. Do not apply
scaling, normalization, saturation, or rounding. The output bins must be
produced in order `X0`, `X1`, `X2`, `X3`.

TIMING AND CONTROL:
- `rst` is synchronous and active-high.
- After the fourth input sample of a frame is accepted, the module must assert
  `out_valid` on the next four clock cycles.
- For example, if the 4th input sample is accepted on cycle N, then the first
  valid output on cycle N+1 must already be `X0` (not an uninitialized value
  and not `X1`).
- While `out_valid` is high, `out_real` and `out_imag` must present `X0`,
  `X1`, `X2`, and `X3` on successive cycles.
- The evaluator will not begin a new input frame until the previous output
  sequence has completed.


## Interface Specification
Module Name: fft4_frame
Ports:
  - input 1 clk // Clock signal
  - input 1 rst // Synchronous reset, active high
  - input 1 in_valid // High when in_real and in_imag contain a valid input sample
  - input 12 in_real // Real component of the input sample, signed two's-complement
  - input 12 in_imag // Imaginary component of the input sample, signed two's-complement
  - output 1 out_valid // High when out_real and out_imag contain a valid FFT output bin
  - output 14 out_real // Real component of the output bin, signed two's-complement
  - output 14 out_imag // Imaginary component of the output bin, signed two's-complement

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module fft4_frame` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable