Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a synchronous heart-rate estimator that reports beats per
minute (BPM) from a stream of detected heartbeat events.

Each rising edge of `clk` represents one 50 ms sample period. The
input `peak_in` is a debounced one-cycle pulse that indicates one
detected heartbeat at that sample. When `peak_in` is low, no heartbeat
event occurred in that sample period.

OUTPUT DEFINITION:
- The BPM estimate is based on a sliding window covering the most
  recent 100 sampled cycles, including the current cycle.
- `bpm_out` must equal 12 times the number of heartbeat events present
  in that 100-sample window. This corresponds to converting the count
  from a 5-second window into beats per minute.
- The module must update the estimate every clock cycle after sampling
  the current `peak_in` input.

VALIDITY RULES:
- `bpm_valid` remains LOW until the module has observed 100 sampled
  cycles since reset was last asserted.
- While `bpm_valid` is LOW, `bpm_out` must be 0.
- Once `bpm_valid` becomes HIGH, it remains HIGH until the next reset.

INPUT GUARANTEES:
- Each asserted `peak_in` represents exactly one heartbeat event.
- The testbench will not present two heartbeat events closer than
  4 clock cycles apart.

RESET:
- `rst` is synchronous and active-high.
- On reset, clear all stored history, restart the window-fill process,
  drive `bpm_out` to 0, and deassert `bpm_valid`.


## Interface Specification
Module Name: bpm_calculator
Ports:
  - input 1 clk // Clock signal; each cycle represents one 50 ms sample period
  - input 1 rst // Synchronous active-high reset
  - input 1 peak_in // One-cycle pulse indicating a detected heartbeat event
  - output 1 bpm_valid // High when a full 100-sample window has been observed since reset
  - output 9 bpm_out // Unsigned BPM estimate for the current 100-sample window

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module bpm_calculator` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable