Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a synchronous PWM (Pulse-Width Modulation) generator with
complementary outputs and configurable dead-time insertion, suitable
for driving a half-bridge power stage.

All outputs (`pwm_high`, `pwm_low`) must be registered — updated
synchronously on the rising edge of `clk`. They must not be driven
by combinational logic.

PWM COUNTER:
- When `enable` is HIGH, an internal 8-bit counter runs
  0, 1, 2, ..., `period - 1`, 0, ...
- `period` is guaranteed to be in the range 1 to 255.
- On each rising clock edge, the module evaluates the raw PWM state
  from the current counter value and determines outputs, then
  advances the counter for the next cycle.
- The raw PWM state is HIGH when the counter value is strictly less
  than `duty`, and LOW otherwise.
- If `duty` is 0, the raw PWM state is always LOW.
- If `duty >= period`, the raw PWM state is always HIGH.

OUTPUT BEHAVIOUR:
- Outside the dead-time interval:
    raw PWM = HIGH -> `pwm_high` = 1, `pwm_low` = 0
    raw PWM = LOW  -> `pwm_high` = 0, `pwm_low` = 1
- Whenever the running raw PWM state changes while `enable` is HIGH,
  both outputs must be driven LOW for exactly `dead_time` full clock
  cycles before the new complementary state appears.
- During dead-time, the counter continues to run normally.
- If `dead_time` is 0, the outputs switch with no all-low gap.

ENABLE AND RESET:
- `rst` is synchronous and active-high.
- On reset, clear the counter, clear any pending dead-time, and drive
  both outputs LOW.
- When `enable` is LOW, hold the counter at 0, clear any pending
  dead-time, and drive both outputs LOW.
- When `enable` becomes HIGH, operation restarts from counter value 0.
  No state from an earlier enabled interval is retained.
- Asserting `enable` is not itself treated as a PWM transition for
  dead-time purposes; only transitions of the running raw PWM state
  insert dead-time.
- On the first clock cycle after `enable` becomes HIGH, the outputs
  must reflect the raw PWM state evaluated at counter value 0
  immediately, with no startup dead-time.


## Interface Specification
Module Name: pwm_deadtime
Ports:
  - input 1 clk // Clock signal
  - input 1 rst // Synchronous active-high reset
  - input 1 enable // Module enable; when low, outputs are forced low and counter is held at 0
  - input 8 period // PWM period in clock cycles (counter counts from 0 to period-1)
  - input 8 duty // Duty cycle value; raw PWM is high when counter < duty
  - input 4 dead_time // Dead-time duration in clock cycles (0 means no dead-time)
  - output 1 pwm_high // High-side PWM output
  - output 1 pwm_low // Low-side PWM output (complementary to pwm_high, with dead-time gaps)

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module pwm_deadtime` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable