Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a fixed-latency population-count unit for 64-bit input data.
On every rising edge of `clk` when `rst` is low, the module samples `data_in` and `threshold`. The module must produce two aligned outputs exactly 2 clock cycles later:
- `count_out`: the number of bits set to 1 in the sampled 64-bit input
  word. The result range is 0 to 64.
- `threshold_exceeded`: asserted when the sampled population count is
  strictly greater than the sampled threshold value.

INTERFACE BEHAVIOUR: - The interface is fully synchronous and accepts a new input every
  cycle.
- There is no valid or ready signal. Outputs are produced every cycle
  after the 2-cycle pipeline delay.
- `threshold_exceeded` must be aligned with the corresponding
  `count_out` result from the same sampled input pair.
- `threshold` is an unsigned 6-bit value in the range 0 to 63.
RESET: - `rst` is synchronous and active-high. - On reset, clear any in-flight pipeline state and drive both outputs
  to zero.
- After reset is deasserted, the first result corresponding to a new
  input appears 2 clock cycles later.


## Interface Specification
Module Name: popcount64_threshold
Ports:
  - input 1 clk // Clock
  - input 1 rst // Synchronous active-high reset
  - input 64 data_in // 64-bit input word
  - input 6 threshold // Unsigned comparison threshold
  - output 7 count_out // Population count result, aligned 2 cycles after input
  - output 1 threshold_exceeded // High when the aligned count is strictly greater than the aligned threshold

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module popcount64_threshold` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable