Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a digital lock controller that monitors keypad presses and asserts an unlock pulse when the correct 4-digit access code has been entered.
The module receives one key event at a time. A key press is accepted only on a rising clock edge when `key_valid` is high. There is no key debounce logic in this task; each accepted key event represents exactly one key press.
ACCESS CODE: - The fixed access code is 2, 4, 6, 2. - `key_code` values 4'h0 through 4'h9 represent decimal digits 0
  through 9.
- `key_code` value 4'hF is a CLEAR key. - Other `key_code` values will not be used by the tests.
MATCHING RULES: - A correct next digit advances the current progress through the code. - If an incorrect digit is entered, the current progress is cleared. - Exception: if the incorrect digit is 2, it must immediately count as
  the first digit of a new attempt.
- If the CLEAR key is entered, any partial progress is cleared and the
  module must not unlock.
- When `key_valid` is low, the module ignores `key_code` and retains
  the current progress.

OUTPUT BEHAVIOUR: - Assert `unlock` for exactly one clock cycle when the final digit of
  the code is accepted.
- The unlock pulse occurs on the clock cycle in which the last correct
  key press is accepted.
- After generating the unlock pulse, the internal progress resets to
  the idle state.

RESET: - `rst` is synchronous and active-high. - On reset, clear all internal state and drive `unlock` low.


## Interface Specification
Module Name: digital_lock_keypad_fsm
Ports:
  - input 1 clk // Clock signal
  - input 1 rst // Synchronous active-high reset
  - input 1 key_valid // High when key_code contains a new key press to accept
  - input 4 key_code // Keypad code: 0-9 for digits, F for CLEAR
  - output 1 unlock // One-cycle pulse asserted when the correct code is completed

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module digital_lock_keypad_fsm` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable