Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a single perceptron (artificial neuron) for binary classification.
The perceptron consists of: - 4 inputs (x0, x1, x2, x3), each an 8-bit unsigned integer. - 4 associated weights: w0=3, w1=-2, w2=4, w3=-1. - A bias term: b=-5.
The neuron computes a weighted sum of its inputs and adds the bias. Then, it applies a step activation function: output 1 if the result is non-negative, otherwise 0.
Outputs: - y: The binary classification result (1-bit). - z: The raw weighted sum before activation (12-bit signed).


## Interface Specification
Module Name: perceptron
Ports:
  - input 8 x0 // Input feature 0, unsigned 8-bit
  - input 8 x1 // Input feature 1, unsigned 8-bit
  - input 8 x2 // Input feature 2, unsigned 8-bit
  - input 8 x3 // Input feature 3, unsigned 8-bit
  - output 1 y // Classification: 1 if weighted sum >= 0 else 0
  - output 12 z // Weighted sum (signed 12-bit)

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module perceptron` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable