Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a discrete PID controller for position control with single-cycle update latency.
The controller computes a control output based on the error between a setpoint and the current position. The internal arithmetic uses scaled fixed-point values to maintain precision and avoid premature saturation.
PID LOGIC:
  1. Error Calculation:
     error = setpoint - position (Handle 17-bit overflow)

  2. PID Terms (All arithmetic is fixed-point, result scaled by >>> 8):
     P_term = (error * Kp) >>> 8
     D_term = ((error - prev_error) * Kd) >>> 8
     
     // Integral Term: Accumulate the SCALED error term
     // integral_next = clamp(integral + ((error * Ki) >>> 8))
     I_term = integral_next

  3. Output:
     output = clamp(P_term + I_term + D_term)

  4. State Update:
     Update integral and prev_error on clock edge.
     Output is registered.

CONSTRAINTS & GENERATION DETAILS: - Latency: Single-cycle. Logic from inputs to registers must complete in one cycle. 
  (No multi-stage pipelining).
- Accumulator: The integral term MUST accumulate the weighted error ((error*Ki)>>8).
  Do NOT accumulate the raw error or the integrator will saturate prematurely.
- Clamping: Both the integral state and the final output must be clamped to
  the 16-bit signed range [-32768, +32767].

FIXED-POINT FORMAT: - Position/Setpoint/Output: 16-bit signed (Q8.8) - Gains (Kp, Ki, Kd): 8-bit unsigned (Q0.8)
REQUIREMENTS: - Updates occur on rising edge of `clk` when `enable` is high. - `rst` clears all internal state and output.


## Interface Specification
Module Name: robot_controller
Ports:
  - input 1 clk // Clock signal
  - input 1 rst // Synchronous reset, active high
  - input 1 enable // Enable PID computation (process when high)
  - input 16 setpoint // Desired position, signed Q8.8 fixed-point
  - input 16 position // Current position, signed Q8.8 fixed-point
  - input 8 kp // Proportional gain, unsigned Q0.8 fixed-point
  - input 8 ki // Integral gain, unsigned Q0.8 fixed-point
  - input 8 kd // Derivative gain, unsigned Q0.8 fixed-point
  - output 16 control_out // PID control output, signed Q8.8 fixed-point (saturated)

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module robot_controller` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable