Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a 16th-order (17-tap) symmetric low-pass FIR filter. Input: 16-bit signed. Output: 32-bit signed. Symmetric coefficients (H[k] = H[16-k]): H0=65, H1=184, H2=419, H3=839, H4=1366, H5=1888, H6=2276, H7=2432, H8=2488.
When in_valid is asserted, process the input sample. Assert out_valid for exactly one cycle when each output is ready. Pipeline depth is unrestricted. Output samples must appear in the same order as inputs. out_valid must be asserted in the exact same clock cycle as the valid sample_out data (not delayed).


## Interface Specification
Module Name: fir_16tap
Ports:
  - input 1 clk
  - input 1 rst
  - input 16 sample_in
  - input 1 in_valid
  - output 32 sample_out
  - output 1 out_valid

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module fir_16tap` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable