Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a clocked hardware module that computes sine and cosine for one input angle.

Goal:
- Compute sin(angle_in) and cos(angle_in) using fixed-point arithmetic.
- This variation is area-oriented (not throughput-optimized).

Fixed-point formats:
- Input `angle_in`: signed 16-bit Q2.14, radians.
  Valid benchmark range: [-pi/2, +pi/2] (about [-1.57, +1.57]).
  Behavior outside this range is undefined.
- Outputs `sin_out` and `cos_out`: signed 16-bit Q1.15.

Interface protocol (simplified for v1):
- `start` is a 1-cycle pulse with a valid `angle_in`.
- Module processes the request and raises `done` for 1 cycle when output is ready.
- `sin_out` and `cos_out` must be valid when `done` is high and remain stable
  until the next `start`.

Accuracy target:
- Compare against ideal mathematical sin/cos at the quantized input angle.
- Required error per output: <= +/-0.00075 (about +/-24 LSB in Q1.15).

Tiny implementation hint:
- A typical area-efficient iterative CORDIC that meets this target uses about
  14-16 iterations with at least ~18-bit internal x/y/z precision.


## Interface Specification
Module Name: cordic_sincos
Ports:
  - input 1 clk // Clock signal
  - input 1 rst // Synchronous reset, active high
  - input 1 start // Start computation (pulse high for one cycle)
  - input 16 angle_in // Input angle, signed Q2.14 fixed-point (radians)
  - output 16 sin_out // Sine result, signed Q1.15 fixed-point
  - output 16 cos_out // Cosine result, signed Q1.15 fixed-point
  - output 1 done // Pulses high for one cycle when result is ready

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module cordic_sincos` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable