Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a CRC-32 generator module with single-cycle throughput. The module continuously updates the CRC-32 value based on valid data bytes.
CRC Configuration (Standard Ethernet/ZIP): - Polynomial: 0x04C11DB7 - Initial Value: 0xFFFFFFFF - Input: Reflected (LSB first) - Output: Reflected - XOR Out: 0xFFFFFFFF
Interface: - Resets to Initial Value. - Process `data_in` when `data_valid` is high. Hold value otherwise. - `crc_out` provides the current CRC value with 1-cycle latency. - `crc_valid` asserts whenever `crc_out` corresponds to valid data (1-cycle latency).
Example: ASCII "123456789" -> 0xCBF43926


## Interface Specification
Module Name: crc32_generator
Ports:
  - input 1 clk // Clock signal
  - input 1 rst // Synchronous reset, active high
  - input 8 data_in // Input data byte
  - input 1 data_valid // High when data_in contains valid data to process
  - output 32 crc_out // Current CRC-32 value (with final XOR applied)
  - output 1 crc_valid // High when crc_out contains a valid CRC (after processing at least one byte)

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module crc32_generator` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable