Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a small Key-Value Store accelerator with GET and PUT operations.
The module maintains an 8-entry cache of key-value pairs. Each key is 8 bits and each value is 16 bits. The store supports two operations:
OPERATIONS: - GET (op=0): Look up the key. If found, output the value and set hit=1.
              If not found, output is undefined and hit=0.
- PUT (op=1): Store the key-value pair. If the key already exists, update
              its value. If the key is new, store it in the first available
              empty slot. If the store is full and the key is new, overwrite
              the oldest entry (slot 0, then 1, etc. in round-robin fashion).

TIMING: - Operations are initiated on the rising edge of clk when enable=1. - Results (value_out, hit) are valid on the next clock cycle. - When enable=0, the store retains its state but outputs are undefined.
RESET: - Synchronous active-high reset clears all entries (all slots become empty).
SLOT MANAGEMENT: - Empty slots are indicated internally (implementation choice). - PUT to an existing key updates in-place without consuming a new slot. - Round-robin replacement starts at slot 0 after reset.


## Interface Specification
Module Name: kv_store
Ports:
  - input 1 clk // Clock signal
  - input 1 rst // Synchronous reset, active high
  - input 1 enable // Operation enable
  - input 1 op // Operation: 0=GET, 1=PUT
  - input 8 key // Key to look up or store
  - input 16 value_in // Value to store (for PUT operation)
  - output 16 value_out // Value retrieved (for GET operation)
  - output 1 hit // 1 if key was found (GET) or stored (PUT)

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module kv_store` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable