Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a combinational packet filter (stateless firewall).
The module examines packet header fields and decides whether to ALLOW or DROP the packet based on the firewall rules below. Rules are evaluated in order; the first matching rule determines the action.
FIREWALL RULES (evaluated in priority order):

  | Priority | Match Condition                          | Action |
  |----------|------------------------------------------|--------|
  | 1        | Source IP in 10.0.0.0/8                  | DROP   |
  | 2        | Source IP in 192.168.0.0/16              | DROP   |
  | 3        | Protocol = ICMP (1)                      | ALLOW  |
  | 4        | Protocol = TCP (6) AND dst_port = 80     | ALLOW  |
  | 5        | Protocol = TCP (6) AND dst_port = 443    | ALLOW  |
  | 6        | Protocol = TCP (6) AND dst_port = 22     | ALLOW  |
  | 7        | Protocol = UDP (17) AND dst_port = 53    | ALLOW  |
  | 8        | (Default) No match                       | DROP   |


## Interface Specification
Module Name: packet_filter
Ports:
  - input 32 src_ip // Source IP address
  - input 16 dst_port // Destination port number
  - input 8 protocol // IP protocol (ICMP=1, TCP=6, UDP=17)
  - output 1 allow // 1 = Allow packet, 0 = Drop packet

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module packet_filter` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable