Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a combinational Longest Prefix Match (LPM) router.
Given a 32-bit destination IP address, the module must determine the best matching route from the routing table below and output the corresponding next-hop port. If the IP matches multiple prefixes, the LONGEST matching prefix wins (most specific route).
ROUTING TABLE (8 entries):

  | Prefix          | Mask Length | Next-Hop Port |
  |-----------------|-------------|---------------|
  | 10.0.0.0        | /8          | 1             |
  | 10.1.0.0        | /16         | 2             |
  | 10.1.1.0        | /24         | 3             |
  | 192.168.0.0     | /16         | 4             |
  | 192.168.1.0     | /24         | 5             |
  | 172.16.0.0      | /12         | 6             |
  | 8.8.8.0         | /24         | 7             |
  | 0.0.0.0         | /0          | 0 (default)   |

OUTPUT BEHAVIOR: - `next_hop` is the port number (0-7) for the longest matching prefix.


## Interface Specification
Module Name: lpm_router
Ports:
  - input 32 ip_addr // Destination IP address (MSB = first octet)
  - output 3 next_hop // Next-hop port number (0-7)

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module lpm_router` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable