Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a combinational IPv4 header field extractor.
The module receives the first 160 bits (20 bytes) of an IPv4 packet header and extracts key fields for downstream processing (e.g., routing, filtering).
IPv4 HEADER FORMAT (first 20 bytes, no options):

  Bits  0-3:   Version (should be 4)
  Bits  4-7:   IHL (Header Length in 32-bit words, should be 5 for no options)
  Bits  8-15:  Type of Service (ignored)
  Bits 16-31:  Total Length (packet size in bytes)
  Bits 32-47:  Identification (ignored)
  Bits 48-50:  Flags (ignored)
  Bits 51-63:  Fragment Offset (ignored)
  Bits 64-71:  TTL (Time to Live)
  Bits 72-79:  Protocol (e.g., TCP=6, UDP=17, ICMP=1)
  Bits 80-95:  Header Checksum (ignored for this task)
  Bits 96-127: Source IP Address
  Bits 128-159: Destination IP Address

The module should: 1. Extract Total Length, TTL, Protocol, Source IP, and Destination IP. 2. Assert `valid` output if Version=4 and IHL=5 (no options case).
INTERFACE: - Input: 160-bit header (bit 0 = MSB of first byte, network byte order). - Outputs: Extracted fields + valid flag.


## Interface Specification
Module Name: ipv4_parser
Ports:
  - input 160 header // Raw IPv4 header (160 bits = 20 bytes, MSB first)
  - output 1 valid // High if Version=4 and IHL=5
  - output 16 total_length // Total packet length in bytes
  - output 8 ttl // Time to Live
  - output 8 protocol // Protocol number (TCP=6, UDP=17, ICMP=1)
  - output 32 src_ip // Source IP address
  - output 32 dst_ip // Destination IP address

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module ipv4_parser` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable