Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a classification output layer for a neural network.
The module receives 6 input logits (signed 8-bit integers) and must identify the class with the highest probability. The probability of class i is given by the Softmax function:
  P(y=i) = exp(x_i) / sum(exp(x_j) for all j)

Your output should be a 6-bit one-hot vector where the bit corresponding to the class with the highest probability is set to 1, and all other bits are 0.
If multiple inputs produce the same maximum probability, the class with the lowest index among them should be selected (e.g., if x0 and x2 are max, set bit 0).
INPUT FORMAT: 6 x 8-bit signed integers (logits). OUTPUT FORMAT: 6-bit one-hot vector.


## Interface Specification
Module Name: hardmax_onehot
Ports:
  - input 8 x0 // Logit 0, signed 8-bit
  - input 8 x1 // Logit 1, signed 8-bit
  - input 8 x2 // Logit 2, signed 8-bit
  - input 8 x3 // Logit 3, signed 8-bit
  - input 8 x4 // Logit 4, signed 8-bit
  - input 8 x5 // Logit 5, signed 8-bit
  - output 6 y_onehot // One-hot output vector (bit i set if x_i maximizes probability)

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module hardmax_onehot` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable