Generate ONLY the Verilog module code for the following specification.

## Problem Description
Implement a direct-mapped cache controller.
CACHE CONFIGURATION: - 256 entries (8-bit index). - 32-bit data words. - Write-through policy.
ADDRESS MAPPING: - Address is 32-bit byte address. - Bits [31:10]: Tag - Bits [9:2]: Index - Bits [1:0]: Offset (Ignored, we handle full words)
INTERFACES: 1. CPU Interface (Blocking):
   - `cpu_req_valid`: Assertion of a request.
   - `cpu_req_ready`: Cache is ready to accept. Handshake happens when invalid writes valid && ready.
   - `cpu_req_rw`: 0 = Read, 1 = Write.
   - `cpu_resp_valid`: Asserted for one cycle when read data is ready.

2. Memory Interface:
   - `mem_req_valid`: Cache requesting memory access.
   - `mem_req_rw`: 0 = Read, 1 = Write.
   - `mem_req_ready`: Memory is ready to accept request. (Assume always 1 for this problem or use valid/ready).
   - `mem_resp_valid`: Memory returning data.

BEHAVIOR: - Hit: Respond with data immediately (1 cycle latency). - Miss: Read from memory, update cache, then respond. - Write: Always write to memory. Update cache if hit.
RESET: - Synchronous active-high reset. Clears all cache entries.


## Interface Specification
Module Name: cache_direct_mapped
Ports:
  - input 1 clk // Clock
  - input 1 rst // Reset
  - input 1 cpu_req_valid // CPU Request Valid
  - input 1 cpu_req_rw // 0: Read, 1: Write
  - input 32 cpu_req_addr // CPU Address
  - input 32 cpu_req_data // CPU Write Data
  - output 1 cpu_req_ready // Cache Ready
  - output 1 cpu_resp_valid // CPU Response Valid
  - output 32 cpu_resp_data // CPU Response Data
  - output 1 mem_req_valid // Memory Request Valid
  - output 1 mem_req_rw // Memory Request Read/Write
  - output 32 mem_req_addr // Memory Request Address
  - output 32 mem_req_data // Memory Request Data
  - input 1 mem_req_ready // Memory Ready
  - input 1 mem_resp_valid // Memory Response Valid
  - input 32 mem_resp_data // Memory Response Data

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module cache_direct_mapped` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable