Generate ONLY the Verilog module code for the following specification.

## Problem Description
Design a single-cycle 8-bit ALU for a small soft processor. The ALU performs arithmetic and logical operations on two 8-bit operands (A and B) based on a 4-bit opcode. The result is 8 bits wide with additional flag outputs.
OPCODE ENCODING:
  0000 (ADD):  Result = A + B
  0001 (SUB):  Result = A - B
  0010 (AND):  Result = A & B
  0011 (OR):   Result = A | B
  0100 (XOR):  Result = A ^ B
  0101 (NOT):  Result = ~A (B is ignored)
  0110 (SHL):  Result = A << 1 (logical left shift, LSB = 0)
  0111 (SHR):  Result = A >> 1 (logical right shift, MSB = 0)
  1000 (INC):  Result = A + 1 (B is ignored)
  1001 (DEC):  Result = A - 1 (B is ignored)
  1010 (CMP):  Result = 8'b0 if A == B, else 8'hFF (comparison)
  1011 (PASS): Result = A (pass-through, B is ignored)
  1100-1111:   Reserved (Result = 8'b0)

FLAGS (active high, updated combinationally based on the result):
  zero:     Set if Result == 8'b0
  negative: Set if Result[7] == 1 (MSB indicates negative in signed representation)
  carry:    Set if ADD, SUB, INC, or DEC produces a carry/borrow out of bit 7.
            For SHL, carry is the MSB (bit 7) before shift.
            For SHR, carry is the LSB (bit 0) before shift.
  overflow: Set if ADD or SUB causes signed overflow (operand signs match but
            result sign differs). For other operations, overflow = 0.

All outputs are purely combinational. There is no clock or reset.


## Interface Specification
Module Name: alu_8bit
Ports:
  - input 8 a // First operand
  - input 8 b // Second operand
  - input 4 opcode // Operation selection (see opcode encoding)
  - output 8 result // Operation result
  - output 1 zero // Zero flag: set when result is zero
  - output 1 negative // Negative flag: set when result MSB is 1
  - output 1 carry // Carry flag: set on carry/borrow for arithmetic ops
  - output 1 overflow // Overflow flag: set on signed overflow for ADD/SUB

## Requirements
- Generate ONLY the Verilog module code
- Do NOT output any reasoning, analysis, scratchpad, or <think> tags
- Start directly with `module alu_8bit` as the first line of your response
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- End with `endmodule`
- Ensure the code is correct and synthesizable