Generate ONLY the Verilog module code for the following specification.

## Problem Description
{{ description }}

## Interface Specification
Module Name: {{ module_name }}
Ports:
{{ ports_formatted }}

## Requirements
- Generate ONLY the Verilog module code
- Do NOT include any testbenches
- Do NOT include any explanations or comments outside the code
- Start with `module {{ module_name }}` and end with `endmodule`
- Ensure the code is correct and synthesizable