You are designing Verilog code for FPGA synthesis. Generate optimized, synthesizable RTL code.

## Problem Description
{{ description }}

## Target Platform
{{ target_platform.device_family }}

## Design Constraints
Your design MUST satisfy these hard constraints:
{% for key, value in constraints.items() %}
- {{ key }}: {{ value }}
{% endfor %}

## Optimization Objective
{{ objective.goal | capitalize }} {{ objective.target }}

## Hardware Design Guidelines
- Target: FPGA synthesis ({{ target_platform.device_family }})
- Optimize according to the objective above
- Use only synthesizable Verilog constructs
- Avoid latches - ensure all paths are fully specified
- Consider using efficient bit manipulation techniques where applicable
- For arithmetic operations, leverage FPGA DSP blocks when beneficial

## Output Requirements
- Generate ONLY the Verilog module code
- Do NOT include testbenches or simulation code
- Do NOT include any explanations outside the code block
- Start with `module` and end with `endmodule`