module streaming_dot_product8 (
    input  wire       clk,
    input  wire       rst,
    input  wire       in_valid,
    input  wire [7:0] a_data,
    input  wire [7:0] b_data,
    input  wire       last_in,
    output reg        result_valid,
    output reg [31:0] result
);
    reg signed [31:0] accum;
    reg signed [31:0] stage0_result;
    reg signed [31:0] stage1_result;
    reg stage0_valid;
    reg stage1_valid;

    wire signed [15:0] product;
    wire signed [31:0] product_ext;
    wire signed [31:0] accum_next;

    assign product = $signed(a_data) * $signed(b_data);
    assign product_ext = {{16{product[15]}}, product};
    assign accum_next = accum + product_ext;

    always @(posedge clk) begin
        if (rst) begin
            accum <= 32'sd0;
            stage0_result <= 32'sd0;
            stage1_result <= 32'sd0;
            stage0_valid <= 1'b0;
            stage1_valid <= 1'b0;
            result_valid <= 1'b0;
            result <= 32'sd0;
        end else begin
            result_valid <= stage1_valid;
            result <= stage1_valid ? stage1_result : 32'sd0;

            stage1_valid <= stage0_valid;
            stage1_result <= stage0_valid ? stage0_result : 32'sd0;

            if (in_valid) begin
                if (last_in) begin
                    stage0_valid <= 1'b1;
                    stage0_result <= accum_next;
                    accum <= 32'sd0;
                end else begin
                    stage0_valid <= 1'b0;
                    stage0_result <= 32'sd0;
                    accum <= accum_next;
                end
            end else begin
                stage0_valid <= 1'b0;
                stage0_result <= 32'sd0;
            end
        end
    end
endmodule