module streaming_histogram64 (
    input wire clk,
    input wire rst,
    input wire in_valid,
    input wire [5:0] sample_in,
    output reg out_valid,
    output reg [5:0] bin_index,
    output reg [15:0] bin_count
);
    localparam STATE_COLLECT = 1'b0;
    localparam STATE_READOUT = 1'b1;

    reg state;
    reg [8:0] sample_count;
    reg [5:0] read_idx;
    reg [15:0] hist_bins [0:63];

    integer i;

    always @(posedge clk) begin
        if (rst) begin
            state <= STATE_COLLECT;
            sample_count <= 9'd0;
            read_idx <= 6'd0;
            out_valid <= 1'b0;
            bin_index <= 6'd0;
            bin_count <= 16'd0;

            for (i = 0; i < 64; i = i + 1)
                hist_bins[i] <= 16'd0;
        end else begin
            out_valid <= 1'b0;
            bin_index <= 6'd0;
            bin_count <= 16'd0;

            if (state == STATE_COLLECT) begin
                if (in_valid) begin
                    hist_bins[sample_in] <= hist_bins[sample_in] + 16'd1;

                    if (sample_count == 9'd255) begin
                        state <= STATE_READOUT;
                        sample_count <= 9'd0;
                        read_idx <= 6'd0;
                    end else begin
                        sample_count <= sample_count + 9'd1;
                    end
                end
            end else begin
                out_valid <= 1'b1;
                bin_index <= read_idx;
                bin_count <= hist_bins[read_idx];

                if (read_idx == 6'd63) begin
                    state <= STATE_COLLECT;
                    read_idx <= 6'd0;
                    sample_count <= 9'd0;

                    for (i = 0; i < 64; i = i + 1)
                        hist_bins[i] <= 16'd0;
                end else begin
                    read_idx <= read_idx + 6'd1;
                end
            end
        end
    end
endmodule