module bloom_filter_membership (
    input wire clk,
    input wire rst,
    input wire req_valid,
    input wire req_insert,
    input wire [15:0] key_in,
    output reg maybe_present
);
    reg [127:0] bloom_bits;
    reg pending_valid;
    reg pending_result;

    wire [6:0] h0;
    wire [6:0] h1;
    wire [6:0] h2;
    wire current_result;

    assign h0 = (key_in ^ (key_in >> 7)) & 16'h007f;
    assign h1 = (key_in + (key_in >> 4) + 16'h002d) & 16'h007f;
    assign h2 = ((key_in << 3) ^ (key_in >> 2) ^ 16'h0053) & 16'h007f;
    assign current_result = bloom_bits[h0] & bloom_bits[h1] & bloom_bits[h2];

    always @(posedge clk) begin
        if (rst) begin
            bloom_bits <= 128'd0;
            pending_valid <= 1'b0;
            pending_result <= 1'b0;
            maybe_present <= 1'b0;
        end else begin
            maybe_present <= pending_valid ? pending_result : 1'b0;

            if (req_valid) begin
                pending_valid <= 1'b1;
                pending_result <= current_result;

                if (req_insert) begin
                    bloom_bits[h0] <= 1'b1;
                    bloom_bits[h1] <= 1'b1;
                    bloom_bits[h2] <= 1'b1;
                end
            end else begin
                pending_valid <= 1'b0;
                pending_result <= 1'b0;
            end
        end
    end
endmodule