# RV32I Micro-Core Test Programs ## Purpose This document defines the small directed programs intended for the eventual `testbench.v` of `rv32_micro_core`. The goals here are: - keep each program short and auditable - use only the supported instruction subset where possible - make expected behaviour observable through memory writes, `halted`, or `trap` - separate assembler-friendly programs from the few raw-word trap vectors The programs below assume instruction memory starts at byte address 0 and that the core begins execution from `PC = 0` after reset. ## Conventions - Signature region addresses are byte addresses in data memory. - For normal terminating programs, final correctness is checked using: - `halted = 1` - `trap = 0` - exact final values written to selected signature words - For trap programs, correctness is checked using: - `halted = 0` - `trap = 1` - absence of any forbidden store ## Program 1: Halt Smoke Test ### Assembly ```asm ebreak ``` ### Expected Outcome - `halted = 1` - `trap = 0` - no store occurs ## Program 2: Arithmetic, Logic, LUI, and x0 ### Intent Exercise `LUI`, `ADDI`, `ADD`, `SUB`, `AND`, `OR`, `XOR`, and confirm that writes to `x0` are ignored. ### Assembly ```asm addi x10, x0, 256 lui x1, 0x12345 addi x2, x0, 21 addi x3, x0, 10 add x4, x2, x3 sub x5, x2, x3 and x6, x4, x5 or x7, x5, x1 xor x8, x7, x1 addi x0, x0, 99 sw x1, 0(x10) sw x4, 4(x10) sw x5, 8(x10) sw x6, 12(x10) sw x7, 16(x10) sw x8, 20(x10) sw x0, 24(x10) ebreak ``` ### Expected Architectural Results - `x1 = 0x12345000` - `x4 = 0x0000001f` - `x5 = 0x0000000b` - `x6 = 0x0000000b` - `x7 = 0x1234500b` - `x8 = 0x0000000b` - `x0 = 0x00000000` ### Expected Signature Writes - `mem[0x100] = 0x12345000` - `mem[0x104] = 0x0000001f` - `mem[0x108] = 0x0000000b` - `mem[0x10c] = 0x0000000b` - `mem[0x110] = 0x1234500b` - `mem[0x114] = 0x0000000b` - `mem[0x118] = 0x00000000` ### Expected Outcome - `halted = 1` - `trap = 0` ## Program 3: Aligned Load/Store Datapath ### Intent Verify correct aligned `LW` and `SW` semantics, plus one arithmetic and one logical operation on loaded values. ### Initial Data Memory - `mem[0x040] = 0x11223344` - `mem[0x044] = 0x01020304` ### Assembly ```asm addi x10, x0, 64 lw x1, 0(x10) lw x2, 4(x10) add x3, x1, x2 xor x4, x1, x2 addi x11, x0, 288 sw x1, 0(x11) sw x2, 4(x11) sw x3, 8(x11) sw x4, 12(x11) ebreak ``` ### Expected Architectural Results - `x1 = 0x11223344` - `x2 = 0x01020304` - `x3 = 0x12243648` - `x4 = 0x10203040` ### Expected Signature Writes - `mem[0x120] = 0x11223344` - `mem[0x124] = 0x01020304` - `mem[0x128] = 0x12243648` - `mem[0x12c] = 0x10203040` ### Expected Outcome - `halted = 1` - `trap = 0` ## Program 4: Branch Loop ### Intent Verify both taken and not-taken branch behaviour with a short loop. The loop computes `3 + 2 + 1 = 6`. ### Assembly ```asm addi x10, x0, 320 addi x1, x0, 0 addi x2, x0, 3 addi x3, x0, 1 beq x2, x0, fail loop: add x1, x1, x2 sub x2, x2, x3 bne x2, x0, loop beq x1, x1, done addi x4, x0, 99 done: sw x1, 0(x10) sw x2, 4(x10) ebreak fail: addi x4, x0, 77 sw x4, 8(x10) ebreak ``` ### Expected Architectural Results - `x1 = 0x00000006` - `x2 = 0x00000000` - the `fail` path is not taken ### Expected Signature Writes - `mem[0x140] = 0x00000006` - `mem[0x144] = 0x00000000` - `mem[0x148]` must remain unchanged ### Expected Outcome - `halted = 1` - `trap = 0` ## Program 5: JAL Link and Control Transfer ### Intent Verify that `JAL` writes the correct link address and transfers control to the correct target. The two instructions after `JAL` must be skipped. ### Assembly ```asm addi x10, x0, 352 addi x1, x0, 7 jal x5, target addi x1, x0, 99 addi x1, x0, 88 target: add x2, x1, x1 sw x5, 0(x10) sw x2, 4(x10) ebreak ``` ### Expected Architectural Results - `x1 = 0x00000007` - `x2 = 0x0000000e` - `x5 = 0x0000000c` ### Expected Signature Writes - `mem[0x160] = 0x0000000c` - `mem[0x164] = 0x0000000e` ### Expected Outcome - `halted = 1` - `trap = 0` ## Program 6: Illegal Instruction Trap ### Intent Verify that an unsupported instruction encoding raises `trap` and suppresses all later side effects. ### Assembly This one is intentionally written with a raw word because the benchmark spec requires trapping on unsupported encodings. ```asm addi x10, x0, 384 .word 0x00000000 sw x10, 0(x10) ebreak ``` ### Expected Outcome - `halted = 0` - `trap = 1` - no store occurs at `0x180` ## Program 7: Misaligned LW Trap ### Intent Verify that a misaligned `LW` raises `trap` and prevents later stores. ### Assembly ```asm addi x10, x0, 65 lw x1, 0(x10) sw x1, 0(x0) ebreak ``` ### Expected Outcome - `halted = 0` - `trap = 1` - no store occurs ## Program 8: Misaligned SW Trap ### Intent Verify that a misaligned `SW` raises `trap` and that the misaligned store is not committed. ### Assembly ```asm addi x10, x0, 256 addi x1, x0, 66 addi x11, x0, 258 sw x1, 0(x11) sw x1, 0(x10) ebreak ``` ### Expected Outcome - `halted = 0` - `trap = 1` - `mem[0x100]` must remain unchanged ## Deferred Raw-Word Trap Vectors Two additional trap scenarios from the spec are best added after the assembler-friendly programs above have been validated: - taken `BEQ` or `BNE` with a non-4-byte-aligned target - `JAL` with a non-4-byte-aligned target These are awkward to express with normal labels because standard assembly places labels on instruction boundaries. They are better introduced later as hand-encoded branch/jump instruction words after the rest of the suite is frozen.