module median7_denoiser (
    input wire clk,
    input wire rst,
    input wire signed [11:0] sample_in,
    output reg out_valid,
    output reg signed [11:0] sample_out
);
    reg signed [11:0] history [0:6];
    reg [2:0] sample_count;

    reg signed [11:0] sorted [0:6];
    reg signed [11:0] swap_tmp;
    reg signed [11:0] median_value;

    integer i;
    integer j;

    always @* begin
        for (i = 0; i < 7; i = i + 1) begin
            sorted[i] = history[i];
        end

        for (i = 0; i < 6; i = i + 1) begin
            for (j = 0; j < 6 - i; j = j + 1) begin
                if (sorted[j] > sorted[j + 1]) begin
                    swap_tmp = sorted[j];
                    sorted[j] = sorted[j + 1];
                    sorted[j + 1] = swap_tmp;
                end
            end
        end

        median_value = sorted[3];
    end

    always @(posedge clk) begin
        if (rst) begin
            out_valid <= 1'b0;
            sample_out <= 12'sh000;
            sample_count <= 3'd0;

            for (i = 0; i < 7; i = i + 1) begin
                history[i] <= 12'sh000;
            end
        end else begin
            if (sample_count == 3'd7) begin
                out_valid <= 1'b1;
                sample_out <= median_value;
            end else begin
                out_valid <= 1'b0;
                sample_out <= 12'sh000;
            end

            if (sample_count < 3'd7) begin
                history[sample_count] <= sample_in;
                sample_count <= sample_count + 3'd1;
            end else begin
                history[0] <= history[1];
                history[1] <= history[2];
                history[2] <= history[3];
                history[3] <= history[4];
                history[4] <= history[5];
                history[5] <= history[6];
                history[6] <= sample_in;
            end
        end
    end
endmodule