module interrupt_controller_4src (
    input  wire       clk,
    input  wire       rst,
    input  wire [3:0] irq_req,
    input  wire [3:0] irq_enable,
    input  wire       irq_ack,
    output reg        irq_valid,
    output reg [1:0]  irq_id
);
    reg [3:0] pending;
    reg [3:0] next_pending;

    always @(*) begin
        irq_valid = 1'b1;
        irq_id = 2'd0;

        if (pending[0] && irq_enable[0]) begin
            irq_id = 2'd0;
        end else if (pending[1] && irq_enable[1]) begin
            irq_id = 2'd1;
        end else if (pending[2] && irq_enable[2]) begin
            irq_id = 2'd2;
        end else if (pending[3] && irq_enable[3]) begin
            irq_id = 2'd3;
        end else begin
            irq_valid = 1'b0;
            irq_id = 2'd0;
        end
    end

    always @(posedge clk) begin
        if (rst) begin
            pending <= 4'b0000;
        end else begin
            next_pending = pending;

            if (irq_ack && irq_valid)
                next_pending[irq_id] = 1'b0;

            next_pending = next_pending | irq_req;
            pending <= next_pending;
        end
    end
endmodule