module digital_lock_keypad_fsm (
    input  wire       clk,
    input  wire       rst,
    input  wire       key_valid,
    input  wire [3:0] key_code,
    output reg        unlock
);
    localparam [1:0] S_IDLE = 2'd0;
    localparam [1:0] S_2    = 2'd1;
    localparam [1:0] S_24   = 2'd2;
    localparam [1:0] S_246  = 2'd3;

    reg [1:0] state;

    always @(posedge clk) begin
        if (rst) begin
            state <= S_IDLE;
            unlock <= 1'b0;
        end else begin
            unlock <= 1'b0;

            if (key_valid) begin
                if (key_code == 4'hF) begin
                    state <= S_IDLE;
                end else begin
                    case (state)
                        S_IDLE: begin
                            if (key_code == 4'd2)
                                state <= S_2;
                            else
                                state <= S_IDLE;
                        end

                        S_2: begin
                            if (key_code == 4'd4)
                                state <= S_24;
                            else if (key_code == 4'd2)
                                state <= S_2;
                            else
                                state <= S_IDLE;
                        end

                        S_24: begin
                            if (key_code == 4'd6)
                                state <= S_246;
                            else if (key_code == 4'd2)
                                state <= S_2;
                            else
                                state <= S_IDLE;
                        end

                        S_246: begin
                            if (key_code == 4'd2)
                                unlock <= 1'b1;
                            state <= S_IDLE;
                        end

                        default: begin
                            state <= S_IDLE;
                        end
                    endcase
                end
            end
        end
    end
endmodule