`timescale 1ns / 1ps

module register_file_2r1w (
    input  wire        clk,
    input  wire        rst,
    input  wire [4:0]  raddr1,
    input  wire [4:0]  raddr2,
    output wire [31:0] rdata1,
    output wire [31:0] rdata2,
    input  wire        we,
    input  wire [4:0]  waddr,
    input  wire [31:0] wdata
);
    reg [31:0] regs [0:31];
    integer i;

    // Synchronous write and synchronous reset
    always @(posedge clk) begin
        if (rst) begin
            for (i = 0; i < 32; i = i + 1) begin
                regs[i] <= 32'b0;
            end
        end else if (we && (waddr != 5'd0)) begin
            regs[waddr] <= wdata;
        end
    end
 
    // Combinational reads with write-through on collision.
    // Register 0 is hardwired to zero.
    assign rdata1 = (raddr1 == 5'd0) ? 32'b0 :
                    ((we && (waddr == raddr1) && (waddr != 5'd0)) ? wdata : regs[raddr1]);
    assign rdata2 = (raddr2 == 5'd0) ? 32'b0 :
                    ((we && (waddr == raddr2) && (waddr != 5'd0)) ? wdata : regs[raddr2]);

endmodule